➀ The semiconductor industry is experiencing transformative growth potential.

➁ Chiplets, artificial intelligence, and advanced packaging are driving this growth.

➂ Foundry capacity is being pushed as a result.

➀ ASML and imec have signed a new strategic partnership agreement, focusing on research and sustainability.

➁ The agreement aims to deliver valuable solutions in two areas: advancing the semiconductor industry and developing sustainable innovation initiatives.

➂ The collaboration includes ASML's full product portfolio, focusing on high-end nodes and advanced technologies.

➀ Huzhou team secures hundreds of millions in financing to break international chip packaging monopoly;

➁ Jingtong Technology, a wafer-level fan-out packaging and Chiplet integration solution provider, focuses on advanced packaging technology;

➂ The market for advanced packaging is growing rapidly, with fan-out packaging and Chiplet integration expected to see significant growth.

➀ The semiconductor packaging and testing industry is crucial in the semiconductor supply chain, with traditional giants like OSAT facing challenges from advanced packaging technologies.

➁ Companies like OSAT leaders such as OSAT, Amkor, and Chipmos are expanding globally and focusing on advanced packaging to maintain their competitive edge.

➂ Key strategies include overseas expansion, investment in new factories, and technological innovation to meet the growing demand for advanced packaging.

➀ Hybrid bonding is gaining attention in advanced packaging for its ability to provide the shortest vertical connections between chips with similar or different functions, as well as better thermal, electrical, and reliability results.

➁ Despite some chip manufacturers adopting hybrid bonding in large-scale manufacturing, the high cost of the process makes it unsuitable for mass adoption. Challenges include better copper dimple uniformity, faster wafer-to-chip placement, and better alignment, multiple bonding and debonding carriers (which increase costs), and low-temperature annealing capabilities.

➂ The development of AI chips and modules is a significant driver for hybrid bonding and advanced packaging. High-performance and high prices of these chips help to drive industry development.

➀ TSMC's CoWoS capacity will double in 2024 and 2025, but demand will continue to exceed supply;

➁ The CoWoS expansion wave is expected to extend into 2026, benefiting equipment suppliers for the next two to three years;

➂ Advanced packaging currently accounts for 7-9% of TSMC's revenue, with expected growth to outpace the company's average over the next five years;

➃ TSMC's CoWoS monthly production capacity is expected to reach 35,000 to 40,000 wafers this year, and surge to 80,000 wafers per month next year;

➄ Strong demand from major AI customers is driving capacity needs, potentially reaching 140,000 to 150,000 wafers per month by 2026.

➀ TSMC is the leading player in the semiconductor industry.

➁ Advanced packaging is becoming a key technology path for chip performance improvement.

➂ TSMC is expected to become the largest packaging service provider with the rapid adoption of Chiplet architecture.

➃ TSMC has invested heavily in advanced packaging technology, with capacity set to grow significantly.

➄ TSMC's CoWoS, InFO, and SoIC technologies are driving the company's leadership in advanced packaging.

➅ TSMC is expanding its capacity to meet the increasing demand for advanced packaging.

➆ TSMC is also investing in optical packaging technology to meet the growing bandwidth needs.

➀ The evolution of semiconductor packaging from 1D PCB design to wafer-level 3D hybrid bonding;

➁ The core technologies of 2.5D and 3D packaging, including various interlayer materials;

➂ The advantages and challenges of each technology, such as Si interlayer, organic interlayer, glass interlayer, and Cu-Cu hybrid bonding;

➃ Key market trends like larger interlayer area, panel-level packaging, and glass interlayer adoption;

➄ The importance of HBM hybrid bonding and CPO in enhancing I/O bandwidth and reducing energy consumption;

➅ The significance of advanced packaging in HPC, 5G/6G, and consumer electronics markets.

➀ Chiplet technology breaks down components from a single system-on-chip (SoC) into multiple small chips (chiplets) with specific functions, and then interconnects them using advanced packaging technology to form a system-in-package (SiP). Advanced packaging technology enhances Chiplet design and performance in terms of interconnect density, signal transmission optimization, thermal performance improvement, reduction of process dependency, and heterogeneous integration, accelerating chip design and application deployment.

➁ With the continuous improvement of chip performance, Chiplet design requires higher signal transmission speed from the substrate. Traditional substrates struggle to meet this demand, but glass substrates offer faster signal transmission rates, lower dielectric losses, and higher interconnect density, providing faster signal transmission channels for Chiplet chips. Additionally, glass substrates have larger packaging sizes and good mechanical stability, allowing for more chiplets in the same area, facilitating large-scale integration of Chiplets and enabling more complex system-in-package designs to meet the performance requirements of high-performance computing and artificial intelligence.

➂ On October 18th at 19:30, the 11th 'Xing Xing Chiplet and Advanced Packaging Public Lecture' will feature a talk by Ma Xiaobo, President of Hunan YueMo Research Institute, titled 'Glass Substrate Chiplet Advanced Packaging and Multi-Physical Field Simulation'. Ma will discuss the prospects and industry status of Chiplet advanced packaging technology, share the application advantages of glass substrates in advanced packaging, and focus on multi-physical field simulation for glass substrate Chiplet advanced packaging and the application and future development trends of deep learning in advanced packaging simulation.

➀ TSMC's HBM4 memory launch brings significant changes, with the most noticeable being the expansion of memory interfaces from 1024 to 2048 bits;

➁ TSMC revealed details about base die for HBM4 manufacturing using improved versions of its N12 and N5 processes at the 2024 European Technology Symposium;

➂ TSMC plans to adopt two different manufacturing processes, N12FFC+ and N5, for the first batch of HBM4 product packaging;

➃ TSMC is working with major HBM memory suppliers like Micron, Samsung, and SK Hynix to integrate HBM4 memory technology using advanced process nodes;

➄ TSMC's N12FFC+ process is suitable for achieving HBM4 performance, allowing memory manufacturers to build 12-Hi (48GB) and 16-Hi (64GB) stacks with over 2TB/s bandwidth;

➅ TSMC's N5 process will integrate more logic functions, reduce power consumption, and provide higher performance with very small interconnect spacing, enabling HBM4 direct 3D stacking on logic chips.